Solid-state devices are well known to have reliability and performance which are strongly related to the temperature of the solid-state die. A transistor or other solid-state or semiconductor device operated at a temperature in excess of its rated temperature experiences significant performance degradation, and its operating lifetime can also be significantly reduced or the device may be irreparably damaged. Most semiconductor and solid-state devices are distributed in a protective package containing the semiconductor or solid state device. The user (a design engineer making higher-level equipment) works with the packaged solid-state device or semiconductor, which is often referred to as though it was simply the semiconductor or solid state device itself. Such packaged solid state devices have electrical and thermal characteristics that are specified by the manufacturer. The user receives or acquires information relating to the maximum temperature of the package, possibly the thermal resistance between the exterior of the package and the chip or die contained therein, maximum allowable voltages, leakage currents, and the like. The user, armed with this information, decides on a physical and thermal mounting method for the packaged device taking into account the expected operating temperature of the device in view of the power dissipated in the device, the thermal resistance between the device and its package, and between the package and the ultimate heat sink or ambient temperature. Many solid-state devices operate with substantially constant electrical power, so the power dissipated in the device remains relatively constant. In such a situation, even a sensitive device may be adequately protected by a thermal sensor connected to the package of the device or a location thermally more remote, connected so that an over-temperature condition results in shutdown of power to the device.
Some modern power solid state devices, such as transistors, are used at high or “RF” frequencies in radar transmitter applications in which the applied power is pulsatory, and in which the applied pulse duration varies from moment to moment in response to range and other requirements of the radar system. Such transistors are often operated near the temperature limits of their capability for maximum performance, with the result that slight variations of temperature may degrade the expected performance or tend toward early failure. Transient thermal performance limitations are imposed by the desire to maintain semiconductor die temperature below the maximum tolerable temperature, however defined, which is usually a maximum of 150° C., while at the same time achieving maximum RF output power with minimum pulse-to-pulse phase variation. Under these conditions, monitoring the temperature of the device package or a thermally remote location may not be sufficient to adequately preserve and protect the device.
There are numerous factors which come into consideration when designing and optimizing performance of the transient temperature behavior associated with solid-state devices, and particularly RF solid-state devices. These include the thermal time constants within the solid-state device itself, including die attach methods, gate pitch spacing, die thickness, and baseplate metal/packaging considerations. Additional considerations include the characteristics of the device-package-to-ambient (heat sink) thermal path. In addition, the pulse width (duration), duty cycle (duty), and RF conversion efficiency must be considered. The ability to analyze transient performance characteristics for widely variable pulse widths and duty cycles as encountered in multifunction radar further compounds the problem of determining and accounting for worst-case performance limitations associated with the pulsewidth, duty cycle, and pulse-to-pulse phase repeatability, which is driven by pulse-to-pulse temperature variation of the solid-state device. Finite-element analysis has been employed to aid in making such determinations, but is limited, at least in part, by the large number of finite elements which are required to suitably model flow, particularly for the fine element structures used in RF transistors and devices. Finite-element modeling can consume many CPU hours to determine steady-state pulse-to-pulse peak temperature excursions for constant-duty waveforms. The result of the finite element analysis is used in conjunction with worst-case thermal analysis to select thermal protective devices such as bi-metallic switches, biased diode junction monitors, or thermocouple/thermistor monitor circuits, which are placed on heatsinks external to the actual solid state device or die. The thermal decoupling between the thermal protective devices and the actual solid-state device may result in protective performance which does not allow the solid-state device to operate continuously near its maximum allowable temperature, so the device is operated at a lower temperature, which is also a lower power level condition. Operation at higher power and near the maximum allowable temperature, which is desirable from a performance point of view, in turn may require the use of additional monitors to limit pulse width and duty rates to protect the transmit functions from degradation or failure due to excursions above the maximum allowable temperature of the solid-state device.
Improved thermal protection arrangements for solid-state devices are desired.